Hybrid CMOS/Nanodevice Circuits with Tightly Integrated Memory and Logic Functionality

We propose hybrid CMOS/nanodevice circuits which have potentials to perform massively parallel high throughput computations and in particular suitable for pattern matching. The performance advantage of novel circuits is mainly due to very high density of nanoscale devices and very tight and synergetic integration of memory and logic functionalities. The tight integration is enabled by high communication bandwidth of areadistributed interface between the nano and CMOS subsystems, while the synergy is due to flexible resource allocation allowing to use nanodevices either as a ternary content addressable memory cell or to implement programmable logic/interconnect.